Rescuing a Stalled or Failed Hardware Project: Audit, Takeover and Costs

Figures are Rapid Circuitry planning estimates from our design review work and are consistent with our cost benchmarks. Actual scope depends on how much documentation exists and how many failure modes there are.

Projects rarely fail in one day. These signs usually appear months before the vendor stops responding:

• Dates slip repeatedly and each slip comes without a root cause or a revised plan.
• Boards have been “almost working” for more than one cycle — random resets, rails that droop, radios that drop the connection.
• You have never seen the schematic, the repository or the issue tracker.
• The BOM contains parts marked not-recommended-for-new-designs, end-of-life, or with lead times of many months.
• There is no written test plan, so nobody can say which requirements have been verified.
• Pre-compliance or certification tests failed and the fix proposed is “try again”.
• One engineer holds all the knowledge and is unavailable.
• Early units in the field come back with the same failure.

1. Freeze scope. No new features until the existing design works.
2. Secure access. Repositories, cloud accounts, app-store listings, domain names, component distributor accounts and the FCC grantee code (the FCC ID belongs to whoever holds the grantee code).
3. Collect every board, including failed and reworked ones, with a label saying what was changed on each.
4. Write a symptom log: what fails, how often, under which conditions (battery level, temperature, radio activity, USB connected or not).
5. Read your contract for IP assignment, deliverables and what has been paid for. This decides what you can demand.
6. Book an independent audit before approving further spend with anyone, including the original vendor.

The difference between a two-week rescue and a four-month redesign is usually whether you hold editable source files. PDFs and Gerbers show what was built; they cannot be edited efficiently.

Ask for manufacturing data in a format that carries attributes, such as Gerber X2 or IPC-2581, rather than a loose set of legacy Gerbers. See our glossary entries on Gerber files and bills of materials.

A useful audit is structured and written, so you can act on it with any team. At Rapid Circuitry it runs in six steps:

1. Intake: requirements, symptom log, files and boards. Reproduce the failure on the bench before theorising.
2. Schematic review: power tree and sequencing, regulator stability, decoupling, reset and boot-strap pins, level shifting, protection (ESD, reverse polarity, surge), component ratings and derating.
3. Layout review: stack-up and return paths, switching-regulator hot loops, decoupling placement, clock and high-speed routing, RF keep-outs and antenna ground, thermal paths, DFM and testability.
4. BOM review: lifecycle status, lead time, single-source risk, grade (commercial vs industrial/automotive), and substitutions that differ from the design intent.
5. Firmware review: architecture, watchdog and brown-out handling, error paths, interrupt and power-mode handling, update and rollback safety, and whether the build is reproducible.
6. Measurements and report: rail ripple and transients, current profile, clocks, RF output where relevant; then a report ranking every finding by severity with a proposed fix and its cost.

The cheapest time to run the schematic step is before layout. On a six-axis robotic-arm motor-controller board, a pre-layout audit found and fixed 14 critical or high-severity errors while they were still edits to a drawing, not respins.

Many of these can be fixed with rework — changing component values, adding capacitance, cutting and jumping a trace — to prove the fix before paying for a respin. Rework on the bench should follow good practice such as the IPC-7711/7721 rework and repair guidelines, and every change must be recorded against the board’s serial number.

EMC and ESD failures

Emissions failures against limits such as those in CISPR 32 (EN 55032 in Europe, similar to FCC Part 15 Class B in the US) are usually traced by matching the failing frequencies to a source: switching-regulator harmonics, MCU or memory clocks, display or camera interfaces, or cables acting as antennas. We use near-field probes and a spectrum analyser on the bench to find the source and coupling path, then fix in order of cost:

1. Firmware and clock changes (spread-spectrum clocking, slower edges, disabling unused peripherals).
2. Filtering at the cable entry: common-mode chokes, ferrites, filter capacitors.
3. Grounding, cable shielding and enclosure changes.
4. A layout respin for return paths, stack-up or regulator placement — only if the cheaper steps cannot close the margin.

ESD failures under IEC 61000-4-2 are usually fixed by adding or relocating TVS diodes at the connector, improving the discharge path to ground, and making firmware recover from upsets instead of locking up. Our compliance testing service runs these pre-compliance scans before a paid lab session.

Field returns

Sort returns into design faults, manufacturing faults and misuse before fixing anything. Record serial numbers, firmware versions and build dates; look for clusters. Failure analysis may need X-ray, cross-sectioning or thermal imaging. A structured 8D report (containment, root cause, corrective and preventive action) keeps the fix from being a guess and gives your customers a documented answer.

• Put the deliverables list and IP assignment in the contract, with files delivered at every milestone, not only at the end.
• Host the repositories in your own organisation and give the vendor access, not the other way round.
• Insist on a design review before each fabrication release; our DFM checklist is a good starting point.
• Keep accounts (cloud, app stores, FCC grantee code, distributors) in your company’s name.
• Budget for pre-compliance testing during DVT rather than discovering EMC problems at the certification lab.

For the full stage-by-stage plan, see our hardware product development roadmap, and for vendor selection, the partner-selection guide.

We work with inherited KiCad, Altium and other native design files and existing firmware repositories, and we start with a fixed-price audit so you know what is salvageable before committing to more. The team covers design review, PCB design, firmware and pre-compliance testing in one place, so fixes are implemented by the people who found them. Rapid Circuitry was founded in 2020 in Hyderabad, India, and has a team of 25+ engineers.

1. Ucamco — The Gerber Layer Format Specification — Gerber X2 attributes for fabrication data (checked September 2026)
2. IPC-2581 Consortium — IPC-2581 open data exchange — single-file PCB manufacturing data (checked September 2026)
3. IEC 61000-4-2 — ESD immunity test — IEC webstore entry (checked September 2026)
4. CISPR 32 — EMC of multimedia equipment, emission requirements — basis of EN 55032 (checked September 2026)
5. FCC — Equipment authorization and grantee codes — who holds an FCC ID (checked September 2026)

Audit, respin and redesign cost ranges are Rapid Circuitry planning estimates, stated with their assumptions above.

• Hardware product development roadmap
• Choosing a development partner
• DFM checklist
• Firmware development cost guide
• EU and US market access for connected devices
• Design review service