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DFM Checklist for PCB Design

A comprehensive Design for Manufacturability checklist covering every critical check before you submit Gerbers to your CM.

8 min read41 checklist itemsUpdated March 2026
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Design for Manufacturability (DFM) is the practice of designing a PCB so that it can be reliably built at your target contract manufacturer (CM). Poor DFM leads to low yield, expensive re-spins, and delayed product launches. This checklist covers the most impactful checks across six categories — use it before every Gerber release.

Items marked Critical represent failures commonly caught during CM DFM review that cause costly board re-spins or production delays. Address these first.

Trace & Space Rules

0/7
  • Minimum trace width ≥ 5 mil (standard fab) or per CM specCritical
  • Minimum trace/space ≥ 5/5 mil on signal layersCritical
  • Power traces sized for current: ≥1 oz Cu, ≥20 mil per amp (rule of thumb)Critical
  • Differential pairs routed with matched length and spacing
  • No acute angles (< 90°) on traces — use 45° bends
  • Controlled impedance traces match target stack-up (e.g., 50Ω ±10%)
  • Trace necking under BGAs is within fab capability

Via Design

0/6
  • Via drill size ≥ 0.2 mm; annular ring ≥ 0.1 mm on each sideCritical
  • Via-in-pad: filled and capped (VIPPO) if used under IC padsCritical
  • No vias placed inside SMD pads (unless tented/filled)Critical
  • Thermal relief vias to planes on through-hole pads for soldering
  • Blind/buried vias confirmed with fab capability before design
  • Via keepout enforced under BGAs (min 0.1 mm from via edge to pad edge)

Component Placement

0/8
  • All SMD components within IPC-7351 courtyard boundaries — no overlapsCritical
  • Polarized components (caps, diodes) oriented consistently across boardCritical
  • No components within 5 mm of board edge (3 mm min for SMD)Critical
  • Heavy components (connectors, transformers) have mechanical retention
  • Matched thermal mass for 0201/0402 passives in close pairs to prevent tombstoningCritical
  • ICs with thermal pads have adequate via array to inner plane for heat dissipationCritical
  • Test points accessible from top side; no components within 2.5 mm of test point
  • Component height clearance verified against enclosure/mating PCB constraints

Solder Mask & Silkscreen

0/7
  • Solder mask expansion ≥ 2 mil per side from copper pad edges
  • No solder mask slivers < 4 mil between adjacent pads (NSMD preferred for fine-pitch)Critical
  • Thermal pad solder paste relief pattern per IC datasheetCritical
  • No silkscreen over pads or exposed copperCritical
  • Reference designators legible at 1:1 scale; font height ≥ 40 mil
  • Board revision, part number, and date code on silkscreen
  • Pin 1 indicators and polarity markers present on all relevant components

Panelization & Fiducials

0/6
  • Panel V-score or tab-route score lines specified and documented
  • Minimum 3 global fiducials on panel (ideally 3 per board for small boards)Critical
  • Fiducials: 1 mm copper circle, 3 mm clearance, on all paste/pick-and-place layersCritical
  • Board outline on mechanical layer is closed (no gaps)Critical
  • Edge connectors and castellated holes flagged in fab notes
  • Panelization confirmed with CM before committing to layout

Design Rule Check (DRC)

0/7
  • Zero DRC errors in EDA tool with CM-specific rules loadedCritical
  • ERC (Electrical Rules Check) passed — no unconnected nets, no shortsCritical
  • Netlist comparison (schematic vs layout) passes — no missing connectionsCritical
  • Gerber files reviewed in viewer (e.g., KiCad Gerber viewer, Gerbv) before submissionCritical
  • BOM cross-checked against schematic — all DNP/NF components flagged
  • Pick-and-place (CPL) file generated and reviewed for correct centroid data
  • Stack-up and impedance notes included in fab drawing or readme

Common DFM Pitfalls to Avoid

  • Using 0201 components without matched thermal pad design — causes tombstoning
  • Placing vias directly in IC thermal pads without VIPPO process — causes solder wicking
  • Insufficient solder paste aperture reduction for large thermal pads — causes voiding
  • Forgetting to add assembly fiducials on boards smaller than 50×50 mm
  • Not reviewing Gerbers in a viewer before submission — catches layer assignment errors

Frequently Asked Questions

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