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Semiconductors / AI Hardware / Consumer Electronics

RISC-V AI accelerator: Architecture, RTL and verification for an always-on edge NPU

Architecture, RTL design and UVM verification work on a RISC-V SoC with an integrated neural processing unit for always-on voice, vision and sensor-fusion workloads in battery-powered wearables, designed to a 10 TOPS/W (INT8) efficiency target, plus the model compiler and software stack.

What we did: We contributed architecture exploration, RTL design and UVM verification for the NPU and SoC subsystems, power-intent (UPF) specification, and the LLVM toolchain, TensorFlow Lite Micro kernels and SDK. Physical design, fabrication and silicon results are not claimed in this case study.

Consumer electronics semiconductor company24 months

Published Last reviewed:

10 TOPS/W
NPU efficiency (INT8)
Design target
< 5 mW
Always-on power budget
Design target
256
MAC units in systolic array
UVM
Verification methodology
Illustrative photo: a generic chip package on an evaluation board (not this design; no silicon is claimed)Illustrative image

The challenge

A consumer electronics company developing next-generation smart wearables and hearables needed a custom AI accelerator that could run ML models continuously while fitting a 5 mW always-on budget for small wearable and hearable batteries.

Power budget constraints

Existing AI accelerators consumed 50-200mW for inference, far exceeding the 5mW budget required for always-on operation in small batteries. Duty cycling reduced user experience quality.

Impact: Target: <5mW continuous inferenceClient-reported baseline

Vendor lock-in

Available solutions from major vendors came with restrictive licensing, high royalties per unit, and limited customization options. The client needed full IP ownership for differentiation.

Impact: Per-unit royalties and limited customisationClient-reported baseline

Model flexibility

Fixed-function accelerators couldn't adapt to evolving ML models. The client needed to update algorithms post-deployment without hardware changes for competitive advantage.

Impact: 6-month hardware refresh cyclesClient-reported baseline

Integration complexity

Off-the-shelf solutions required external memory, PMICs, and supporting chips, increasing BOM cost, PCB area, and power consumption for their compact form factor.

Impact: 4-chip solution increasing size by 3xClient-reported baseline

Impact figures describe the situation before the project, as the client reported it to us; we did not measure them.

Our solution

We worked on the design and verification of a RISC-V based SoC with an integrated neural processing unit (NPU) optimized for TinyML workloads, featuring aggressive power gating, in-memory computing elements, and a flexible dataflow architecture.

System architecture

Heterogeneous architecture combining a RISC-V application processor with custom neural accelerator blocks and comprehensive power management.

Application processor

  • Dual-core RISC-V RV32IMFC (custom microarchitecture)
  • 16KB I-cache, 16KB D-cache per core
  • Hardware floating-point unit
  • Custom DSP extensions for signal processing
  • Secure boot and hardware root of trust

Neural processing unit

  • 256 MAC units in systolic array
  • Support for INT4/INT8/INT16 precision
  • On-chip SRAM with in-memory computing
  • Flexible dataflow (weight/output stationary)
  • Hardware activation functions (ReLU, Sigmoid, Softmax)

Memory subsystem

  • 1MB unified on-chip SRAM
  • Intelligent memory controller with compression
  • 4MB external QSPI flash interface
  • DMA engine for zero-copy data movement
  • Memory protection unit for security

Sensor hub & I/O

  • Always-on sensor processor (separate power domain)
  • PDM microphone interface (up to 4 channels)
  • I2S for audio codec
  • SPI/I2C/UART for sensors
  • 12-bit ADC for analog sensors

Power management

  • Integrated PMIC with multiple LDOs
  • Dynamic voltage and frequency scaling
  • Power gating for 8 independent domains
  • Ultra-low-power RTC and wake-up controller
  • Battery fuel gauge integration

Design targets

NPU Performance
≈51 GOPS peak INT8 (256 MACs × 2 ops × 100 MHz; target)
Power Efficiency
10 TOPS/W INT8 (target)
Always-On Power
< 5mW, voice wake + basic inference (target)
Deep Sleep
< 1µA with RTC (target)
Power Domains
8 independently gated
Verification
UVM testbench, formal checks on critical paths

Software stack

  • Custom LLVM toolchain with RISC-V extensions
  • Lightweight RTOS optimized for power management
  • TensorFlow Lite Micro with custom kernels
  • Model compiler with quantization support
  • Power-aware scheduling runtime
  • Secure OTA update mechanism
  • HAL with power state management APIs

TinyML model support

The NPU architecture was optimized for common TinyML workloads while maintaining flexibility for model updates. Accuracy and power figures below are design targets from model evaluation and power modelling, not silicon measurements.

Keyword spotting

DS-CNN (Depthwise Separable CNN)

96% accuracy on custom vocabulary

Design target

8ms inference, <3mW power

Voice activity detection

RNN-based classifier

98% detection accuracy

Design target

Always-on at 0.8mW

Person detection

MobileNetV3-Small variant

92% accuracy at 96x96 resolution

Design target

45ms inference, <15mW power

Gesture recognition

1D CNN on accelerometer data

94% on 12 gesture classes

Design target

5ms inference, <1mW power

Sensor fusion

Multi-input neural network

Activity recognition, context awareness

Continuous at 2mW

Implementation timeline

Phase durations are approximate and cover the main engineering work only, so they add up to less than the 24 months programme.

Phase 1: Architecture & specification

12 weeks
  • Workload analysis and benchmarking
  • Architecture exploration and trade-off studies
  • RTL microarchitecture specification
  • Power and performance modeling

Phase 2: RTL design & verification

32 weeks
  • RTL implementation (Verilog)
  • Comprehensive UVM testbench development
  • Formal verification for critical paths
  • Power intent specification (UPF)

Phase 3: Verification closure & handoff

24 weeks
  • Coverage-driven regression and verification sign-off
  • Synthesis trials for area and power estimates
  • Handoff of the verified RTL and UPF package to the client

Phase 4: Software stack & SDK

16 weeks
  • LLVM toolchain with custom RISC-V extensions
  • TensorFlow Lite Micro kernels and model compiler
  • Pre-silicon simulation environment
  • SDK and documentation completion

Results & impact

Our deliverables were the verified RTL and power intent for the NPU and SoC subsystems, the verification environment, and the software toolchain and SDK. Efficiency and power figures are design targets from power modelling; fabrication and silicon measurements are outside the scope of this case study.

How to read the labels: Design target = an engineering target, not a field measurement; Client-reported baseline = the client's own figure for the situation before the project; we did not measure it. Figures without a label are specifications or project scope.

Energy efficiency

Design target

10 TOPS/W

INT8 NPU efficiency

Always-on power

Design target

< 5 mW

Voice wake plus basic inference

On-device inference latency

Design target

< 10 ms

Keyword spotting class workloads

Technologies used

  • RISC-V
  • NPU RTL
  • UPF power intent
  • TensorFlow Lite Micro
  • Verilog
  • UVM
  • Synopsys Design Compiler
  • LLVM
  • FreeRTOS
  • Hardware Security Module

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